Skills

Hardware Description Languages

Language	Proficiency
SystemVerilog	Full
Verilog	Full
VHDL	Basic
SDC (Synopsys Design Constraints)	Solid
TCL	Solid

EDA & CAD Tools

FPGA: Vivado, Vitis

Open-source ASIC flow: Yosys, OpenROAD, LibreLane

Simulation & verification: Synopsys VCS, Verilator, Icarus Verilog, cocotb

Physical design: Magic VLSI, KLayout, Netgen

Analog: ngspice

FPGA Platforms

Xilinx/AMD UltraScale+ U250, PYNQ-Z2 (Zynq-7000), Basys3 (Artix-7)

ASIC / Physical Design

GlobalFoundries GF180MCU (0.18µm), GDS II, LVS, DRC, Timing Closure, Floorplanning, Place-and-Route, LibreLane/OpenROAD flow

Architecture & Simulation

gem5, Verilator, Icarus Verilog

Software & Scripting

Language	Proficiency
Python	Solid
Bash/Shell	Full
C++	Intermediate
C	Intermediate
C#	Intermediate
TypeScript	Basic
JavaScript	Basic
Rust	Basic

Research Domains

Computer Architecture · VLSI Design · ML Accelerators · ASIC Physical Design · Event-Based Machine Vision · LUT-Based Logic Neural Networks · Cache Prefetching